Intel: USB problem requires new stepping for "Lynx Point" chipsets
In detail, there should be 3.0 devices according to the product change notification when the previous C1 stepping after waking up from the S3 state (suspend to RAM) circumstances not specified cause problems with the detection of USB. All "Lynx Point" imprint be affected, so the desktop versions of B85, H87, Z87, Q85 and Q85, as well as the mobile solutions HM86, HM87 and QM87, and C222, C226 and C224 for server. Despite the new C2 stepping no additional development and adaptation time case for the motherboard but since only metal layers within the chips had been adapted, without making any further changes to the pin assignment.In detail, there should be 3.0 devices according to the product change notification when the previous C1 stepping after waking up from the S3 state (suspend to RAM) circumstances not specified cause problems with the detection of USB. All "Lynx Point" imprint be affected, so the desktop versions of B85, H87, Z87, Q85 and Q85, as well as the mobile solutions HM86, HM87 and QM87, and C222, C226 and C224 for server. Despite the new C2 stepping no additional development and adaptation time case for the motherboard but since only metal layers within the chips had been adapted, without making any further changes to the pin assignment.
The parallels are interesting which become the "Cougar Point" chipsets of Sandy Bridge processors let: already at that time a new stepping to solve the problem had to be filed later, SATA had out of having 3 GB/s interfaces as flawed. Since this only happened after the market launch early 2011, this resulted a large-scale recall and Exchange action at the time.
Source: Intel